Flash memory is a nonvolatile memory in which data may be electrically erased and programmed. Flash memory may be used as both random access memory (RAM), in which data may be freely written and deleted, and read only memory (ROM), which may preserve data even when power is not supplied thereto. Thus, flash memory may be widely used as a storage medium for portable electronic devices such as digital cameras, personal digital assistants (PDAs), and MP3 players.
FIG. 1A illustrates a flash memory device 10 having a fixed block size of 128 KB and FIG. 1B illustrates the address structure of the flash memory device 10 illustrated in FIG. 1A. FIG. 2A illustrates a flash memory device 20 having a fixed block size of 256 KB and FIG. 2B illustrates the address structure of the flash memory device 20 illustrated in FIG. 2A.
Referring to FIGS. 1A, 1B, 2A and 2B, the flash memory devices 10 and 20 may have a multi-plane structure including a plurality of planes Plane 1 and Plane 2. The memory cell array of the flash memory device 10 illustrated in FIG. 1A may include 2048 blocks, each having a size of 128 KB. Each of the blocks of the flash memory device 10 illustrated in FIG. 1A may be located in one of the two planes Plane 1 and Plane 2 and include 64 pages. The blocks of the flash memory device 10 illustrated in FIG. 1A may be addressed in a manner such that two neighboring blocks are located in different planes. Thus, blocks located in the plane Plane 1 may be addressed as Block0, Block2, Block4, . . . , Block2046.
The flash memory device 20 illustrated in FIG. 2A may include 1024 blocks, each having a size of 256 KB. One block of the flash memory device 20 illustrated in FIG. 2A may correspond to two combined blocks respectively located in different planes as illustrated in FIG. 2A. Thus, the blocks of the flash memory device 20 may have a size twice that of the blocks of the flash memory device 10. Each of the blocks of the flash memory 20 may include 128 pages.
FIGS. 1B and 2B respectively illustrate address structures corresponding to memory cell array structures of the flash memory devices 10 and 20 illustrated in FIGS. 1A and 2A. When the flash memory devices 10 and 20 receive a 17-bit external input address, an address controller (not shown) may decode the external input address into a block address and a page address in order to map the external input address to the memory cell array. Accordingly, the address structure corresponding to the flash memory device 10 illustrated in FIG. 1A may have an 11-bit block address and a 6-bit page address, as illustrated in FIG. 1B. The address structure corresponding to the flash memory device 20 illustrated in FIG. 2A may have a 10-bit block address and a 7-bit page address.
As described above, conventional flash memory devices may have fixed block sizes and physically fixed address structures, where the block size of the flash memory devices may not be changed.